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Level Sensitive Scan Design Circuit Testing Technique

IP.com Disclosure Number: IPCOM000044807D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Belani, KG: AUTHOR [+3]

Abstract

When a level sensitive scan design (LSSD) test generation system creates test, it may apply signals to clocks in two manners: 1. Pulsing clock (0 to 1 to 0, same cycle) 2. Stim clock (0 to 1 only) Both types are intermixed for most LSSD parts. This presents a problem to existing testers: the standard test procedure is to connect a given pin to a pulse generator or to a "stim" generator (TGO). If, during testings, we are connected to one generator and need to apply a signal of the opposite type we must dynamically disconnect from one generator and reconnect to the other. Each reconnection uses three local memory locations and requires knowledge of the actual generators assigned to each clock pin, making automatic pattern modification difficult.

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Level Sensitive Scan Design Circuit Testing Technique

When a level sensitive scan design (LSSD) test generation system creates test, it may apply signals to clocks in two manners: 1. Pulsing clock (0 to 1 to 0, same cycle)

2. Stim clock (0 to 1 only)

Both types are intermixed for most LSSD parts. This presents a problem to existing testers: the standard test procedure is to connect a given pin to a pulse generator or to a "stim" generator (TGO). If, during testings, we are connected to one generator and need to apply a signal of the opposite type we must dynamically disconnect from one generator and reconnect to the other. Each reconnection uses three local memory locations and requires knowledge of the actual generators assigned to each clock pin, making automatic pattern modification difficult.

The solution to this problem is to position the clock pulses such that the leading pulse edge is the same under all conditions and whether or not the signal returns to zero is varied. This varying is controlled by a simple LSET RZ instruction to the tester that is independent of actual pulse generator assigned (see diagram). Repositioning the pulses is required to assure adequate time for the effect of the transaction to propagate through the logic and is not a problem in today's technologies since internal propagation delays are considerably smaller than deployed tester cycles.

The solution has the following advantages over the current testing methodology:

a)LSET RZ tak...