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CMOS Voltage Level Generator for Liquid Crystal Displays

IP.com Disclosure Number: IPCOM000044894D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Rugila, G: AUTHOR

Abstract

The driving voltages to a liquid crystal display must be waveforms made up of voltages of different levels. The circuit of Fig. 1 employs complementary metal-oxide semiconductor (CMOS) field-effect transistors to alternately activate two voltage divider networks to provide four output levels.

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CMOS Voltage Level Generator for Liquid Crystal Displays

The driving voltages to a liquid crystal display must be waveforms made up of voltages of different levels. The circuit of Fig. 1 employs complementary metal-oxide semiconductor (CMOS) field-effect transistors to alternately activate two voltage divider networks to provide four output levels.

One control input A achieves four output levels; Ground, 1/3V; 2/3V, and V. All of the resistors in the circuit, R1 through R4, are of equal value, and the transistors are alternately N-channel and P-channel field-effect transistors, as shown.

With input A at +V, the supply potential, all P-channel devices are gated off while all N-channel devices are switched on. T2 then provides a short circuit between nodes O1 and I1, resulting in a divider network across +V of R1, R3, and R4. Output O1 therefore is at 2/3V, and node I2 is at 1/3V. Input A also gates T4 on, and output O2 is thereby connected to the 1/3V at node I2, while T6 is also gated on, thereby discharging output O3 to ground.

A signal regularly alternating between +V and ground is applied to input A. The signal on A and the output signals realized are shown in Fig. 2. On the remaining half cycle, when A is at ground, all the N-channel devices are gated off and all the P-channel devices are gated on. T1 then is a short circuit past R1 and a divider network of R2, R3 and R4 appears across +V. Output O1 is at V. Output O2 is connected to node I1 through T3, which...