Browse Prior Art Database

Dual Gate CMOS Logic

IP.com Disclosure Number: IPCOM000044900D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Archer, DW: AUTHOR

Abstract

A multiple gate CMOS structure is disclosed wherein for a particular channel-type device, two gate electrodes are superimposed over the channel region.

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Dual Gate CMOS Logic

A multiple gate CMOS structure is disclosed wherein for a particular channel-type device, two gate electrodes are superimposed over the channel region.

In Fig. 1a, a top view is shown of a first FET device 10 wherein two gates 1 and 2 are arranged so as to make a serial conduction path between the source 3 and the drain 4. A circuit schematic symbol is shown in Fig. 1b for the device 10.

In Fig. 2a, there is shown a top view of a second device 20 wherein two gates 5 and 6 are arranged to provide a parallel conducting path between the source 7 and the drain 8. A circuit schematic symbol of the device 20 is shown in Fig. 2b.

Fig. 3 illustrates how a P channel FET device 20 with two parallel gates can be connected with an N channel FET device 10 with two serial gates so as to perform a two-input NAND logical function.

Fig. 4 illustrates how a P channel FET device 10' with two serial gates is connected to an N channel FET device 20' with two parallel gates to form a two- input NOR logical function.

Fig. 5 illustrates how a three-device flip-flop circuit can be formed by a conventional CMOS inverter 30 having a P channel FET device 32 with a single gate and an N channel FET device 34 with a single gate, their gates connected In common to one of the gates 2 of the two-gate serial-type N channel FET device 10, the other gate 1 of which is connected to the output node of the CMOS inverter 30, as shown in Fig. 5.

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