Browse Prior Art Database

Bus Protecting Driver with Error Detection

IP.com Disclosure Number: IPCOM000044919D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 71K

Publishing Venue

IBM

Related People

Jordan, A: AUTHOR

Abstract

This article describes a driver circuit for devices in a common bus system. The circuit has parallel driver elements with a common output node. The use of multiple driver elements prevents disruption of bus operation even if one of the driver elements fails. The article also describes online self test circuits for detecting driver element input and output errors.

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Bus Protecting Driver with Error Detection

This article describes a driver circuit for devices in a common bus system. The circuit has parallel driver elements with a common output node. The use of multiple driver elements prevents disruption of bus operation even if one of the driver elements fails.

The article also describes online self test circuits for detecting driver element input and output errors.

Referring to Fig. 1, the circuit includes an array )0 of parallel driver elements, each of which is connected to a common output node 12 through a resistor 14A, 14B... 14N. The common node 12 is connected to a bus 16 shared by a number of terminals or other data processing devices. A receiver 18 for each such device is also connected to bus 16.

The outputs from the individual driver elements in the array 10 are connected to a driver fault detector circuit 20. Driver fault detector circuit 20, every driver element in array 10 and a control error detector circuit 22 all receive a signal at an input node 24. A gating signal at input node 26 is applied both to the driver element array 10 and the control error detector circuit 22. A control check clock signal is applied on line 28 to circuit 22. Under certain conditions, which will be described in more detail below, circuit 22 will reduce a control error signal indicating an error in the signals applied to the driver element array 10. A drive check clock is applied over line 30 to driver fault detector circuit 20. Circuit 20 detects a bad driver element in the array 10 and provides a driver fault signal on its output 32.

Fig. 2 discloses array 10, driver fault detector circuit 20 and control error detector circuit 22 in more detail. The circuit 22 includes a flip-flop 34. The data input to flip-flop 34 is supplied from an OR gate 38, driven by the gating signal or the data signal. The clock input to flip-flop 34 is the logical AND combination of a control check clock signal and the inverse output s...