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Reduction of Punchthrough in Josephson Circuits

IP.com Disclosure Number: IPCOM000044956D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Feder, JD: AUTHOR [+3]

Abstract

In Josephson logic devices the phenomenon of punchthrough is well known. In this phenomenon, devices latch into a state and sometimes do not reset to their zero voltage state when the power supply waveform goes through zero current. In order to reduce the probability of punch through, a dwell is introduced in the power supply waveform in the vicinity of zero current. A circuit is described for introducing this dwell, wherein the Josephson supercurrent is used to supply the dwell.

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Reduction of Punchthrough in Josephson Circuits

In Josephson logic devices the phenomenon of punchthrough is well known. In this phenomenon, devices latch into a state and sometimes do not reset to their zero voltage state when the power supply waveform goes through zero current. In order to reduce the probability of punch through, a dwell is introduced in the power supply waveform in the vicinity of zero current. A circuit is described for introducing this dwell, wherein the Josephson supercurrent is used to supply the dwell.

The circuit, as Is shown in the figure, comprises a shunt 10 connected to the input power line 12. Shunt 10 is comprised of a plurality of Josephson junctions J1, J2...Jk. Each of the shunt Josephson junctions has s resistance R connected across it. The inductor L or transmission line 14 is used to isolate shunt 10 from the capacitance of the Josephson junctions J comprising the regulator 16. Otherwise, this capacitance would appear across shunt 10 and make the shunt junction hysteretic.

The damping resistors R(s) across the shunt junctions have a value such that the junctions J1 - JK are nonhysteretic, so that those junctions cannot punch through. The equivalent logic load is indicated by the resistor R(1).

At low input current, the shunt junctions J1 - Jk are superconducting, and the current in the logic load R(1) is approximately zero. The load current is held at zero until the critical current of the shunt is exceeded, thereby producing...