Browse Prior Art Database

Global Timing and Resetting of NDRO Memory Chip

IP.com Disclosure Number: IPCOM000044960D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Faris, SM: AUTHOR

Abstract

In the Josephson technology NDRO (nondistructive readout) cache memory, the shortest access times and cycle times depend on the organization of the memory chip and on efficient timing and resetting. Typically, pulse generators which have to be set and reset are required, as are short pulse distribution networks. In order to eliminate these pulse generators in the pulse distribution networks, an interface pulse generator (IPC) is used. The IPG is shown in Fig. 1-1, while its circuit symbol is shown in Fig. 1-2.

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Global Timing and Resetting of NDRO Memory Chip

In the Josephson technology NDRO (nondistructive readout) cache memory, the shortest access times and cycle times depend on the organization of the memory chip and on efficient timing and resetting. Typically, pulse generators which have to be set and reset are required, as are short pulse distribution networks. In order to eliminate these pulse generators in the pulse distribution networks, an interface pulse generator (IPC) is used. The IPG is shown in Fig. 1- 1, while its circuit symbol is shown in Fig. 1-2.

The IPC is DC powered, self resetting, and will accept bipolar logic levels on the input line, it includes two Josephson tunneling devices 10, 12, matched impedances Z(o), and two output load resistors R(L). This circuit receives the bipolar input pulses and converts them to short pulses 14. The circuit can be used to provide short pulses in many places in the memory, rather than having to propagate short pulses over long distances. It can also be used to produce pulses in transmission lines with impedance Z(o) by making L(L)/R(L) very large. In order to make the circuit independent of rise times, R(s) may be removed.

In a memory circuit, decoders are used to distinguish between reading, writing a "1" and writing a "0". The addresses, R/W and DATA information are supplied to the address loops through the logic memory interface circuits IPG. These convert the bipolar signal levels into short pulses of appropriate amplitude and duration. In turn, these short pulses are needed throughout the memory chip as a safety measure to insure that loops will not be hung in the voltage state. The IPG circuits can also be used to set the complement address loops, in order to eliminate the need for complement address signals. Another IPG can be used to provide a short pulse to start decoding in a self resetting decoder. This IPG can be triggered by a chip enable signal CE(t) after the binary information has settled in the address loops.

In the read cycle the information store...