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Vertical Partition Test Patterns

IP.com Disclosure Number: IPCOM000044961D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Tsui, F: AUTHOR

Abstract

Vertical partition of the logic of large-scale integration devices, with multiplexer connection of overlap groups to common logic, reduces the complexity of test procedures and reduces the test logical requirement.

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Vertical Partition Test Patterns

Vertical partition of the logic of large-scale integration devices, with multiplexer connection of overlap groups to common logic, reduces the complexity of test procedures and reduces the test logical requirement.

In pattern generation for testing LSI/VLSI logic, one main problem is the excessive size (number of pattern combinations) for large structures. A technique currently used to circumvent this problem is to divide the logic into so- called Test Generation Partitions (TGPs) based on "back-tracing" from each "primary output" (padbound circuit node (CN-output) or Shift Register Latch (SRL) (non-pad fed L-input) to determine all "primary Inputs" (pad-fed CN-inputs) or SRL (non-pad bound L-outputs) to obtain LIPs (logically independent partitions). The LIPs are combined to form TGPs of manageable sizes. A problem encountered frequently, limiting the technique, is due to overlap between TGPs which increases the total block count to be handled by the test generation and fault simulation programs.

Vertical test generation patterns help circumvent the overlap problem and reduce the complexity of test-pattern generation, by introducing a "vertical cut" in the problem-area in the large CN, by inserting multiplexers at the outputs of the overlap-group (which will be called CN star in the following, the "*" indicating node position 1, 2..n, respectively).

The multiplexers are selectively gated by operation mode (OM) signals or, alterna...