Browse Prior Art Database

Improving L2 Performance in a Multilevel Memory Hierarchy

IP.com Disclosure Number: IPCOM000044967D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Pomerene, JH: AUTHOR [+4]

Abstract

In current multilevel memory hierarchies, the accesses to the L2 storage are storage accesses that do not indicate a hit (misses) in the L1 storage.

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Improving L2 Performance in a Multilevel Memory Hierarchy

In current multilevel memory hierarchies, the accesses to the L2 storage are storage accesses that do not indicate a hit (misses) in the L1 storage.

The number of misses from L2 storage can be reduced if all accesses to storage are presented to the L2 store so that it can maintain its directory and reflect actual line usage.

However, in certain multiprocessing configurations, such a load on the L2 store would be impractical.

A subset of the hits on the L1 store is sufficient to derive a reduction in the misses from L2. This subset is the L1 hits other than to the most recently used (MRU) L1 lines. The filtering of L1 hits not broadcast is derived from the bits used to control L1 replacement, so long as the bits identify the MRU line in each congruence class correctly. Any change in the MRU bits forces the access to be transmitted to the L2 storage with a hit or miss indication.

By presenting to L2 not only L1 misses but also the above described subset of L1 hits, a traffic reduction of approximately 12 to 1 is obtained and actual line usage is reflected in the L2 directory.

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