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Browse Prior Art Database

Signature Analysis Testing of a Direct Memory Access Controller

IP.com Disclosure Number: IPCOM000044988D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Davis, GT: AUTHOR [+4]

Abstract

Signature analysis is a useful test technique for verifying the proper operation of cards and troubleshooting faulty cards to determine where the problem resides. In that manner, many cards may be salvaged with simple repair. However, tests utilizing the signature analysis technique are not possible where feedback paths are present. For example, in the case of direct memory access (DMA) chips, the DMA controller is connected to peripheral chips via request and acknowledge lines for one type of feedback and a second type of feedback is found between the DMA controller and the CPU via hold request and hold acknowledge signals. This article describes a combined hardware and software solution to break these feedback loops and make them more testable.

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Signature Analysis Testing of a Direct Memory Access Controller

Signature analysis is a useful test technique for verifying the proper operation of cards and troubleshooting faulty cards to determine where the problem resides. In that manner, many cards may be salvaged with simple repair. However, tests utilizing the signature analysis technique are not possible where feedback paths are present. For example, in the case of direct memory access (DMA) chips, the DMA controller is connected to peripheral chips via request and acknowledge lines for one type of feedback and a second type of feedback is found between the DMA controller and the CPU via hold request and hold acknowledge signals. This article describes a combined hardware and software solution to break these feedback loops and make them more testable.

In order to verify the data and commands sent to the DMA chip for initialization, the DMA channels are disabled and the individual DMA request lines are toggled, thus verifying propagation to the DMA chip. A test point is defined on the product and is used to degate the hold request line to the CPU. In that manner, the individual channels can remain enabled and propagation through the DMA chip can be verified. The read/write lines can be gated and used as a clock to verify data bus contents under portions of the routine not under DMA control.

Once the propagation of DMA request signals has been verified, the circuit shown in the figure is used to generate DM...