Browse Prior Art Database

Programmable Delay Lines in Signature Analysis Testing

IP.com Disclosure Number: IPCOM000044989D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Eggebrecht, LC: AUTHOR

Abstract

This article describes the use of a programmable delay line in both the clock and data lines of a signature analysis test to stress the card under test at the limit of its timing specifications in order to detect marginal timing failures. The delay line may also be used to address the problem of indeterminate signatures due to timing problems, for example, when a clock transition occurs simultaneously with a data transition.

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Programmable Delay Lines in Signature Analysis Testing

This article describes the use of a programmable delay line in both the clock and data lines of a signature analysis test to stress the card under test at the limit of its timing specifications in order to detect marginal timing failures. The delay line may also be used to address the problem of indeterminate signatures due to timing problems, for example, when a clock transition occurs simultaneously with a data transition.

Signature analysis is a common method used to test for proper operation of complex electronic circuits. The electronic circuit is put into a known loop which has no feedback, and selected nodes are tested to see that a specific cyclic redundancy check (CRC) code is generated. Depending on the value and stability of the CRC code, a node can be verified as operating correctly. B The code values are obtained by clocking the status of a node under est into a CRC generator. Clocks are normally chosen such that the node under test does not change as the clock is sampling. Even though signature analysis tests are run at functional speeds, the requirement for a node to be stable at CRC clock time may allow systems to pass tests even though a true timing problem exists.

By providing a programmable delay line in both the clock and data inputs to the code generator, the timing relationship between the node signal and the clock can be varied to specifications in order to stress the circuit. If the si...