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Improved Cycle Rate of Main Memory Write Functions

IP.com Disclosure Number: IPCOM000045000D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 37K

Publishing Venue

IBM

Related People

Grimes, DW: AUTHOR [+2]

Abstract

A technique is described to improve system performance in Memory Write Cycle operations. Memory technologies are restricted by their cycle time specifications (i.e., their cycle time cannot be faster than specified). During consecutive memory cycles, the second cycle cannot be allowed to commence until the specified cycle width of the first cycle has been completed properly. Minimum cycle time specifications insure adequate recovery time for the memory modules' circuits between accesses. System performance is constrained by these memory requirements.

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Improved Cycle Rate of Main Memory Write Functions

A technique is described to improve system performance in Memory Write Cycle operations. Memory technologies are restricted by their cycle time specifications (i.e., their cycle time cannot be faster than specified). During consecutive memory cycles, the second cycle cannot be allowed to commence until the specified cycle width of the first cycle has been completed properly. Minimum cycle time specifications insure adequate recovery time for the memory modules' circuits between accesses. System performance is constrained by these memory requirements.

A memory cycle consists of two sequential operations: (1) the dynamic functional access and (2) recovery of memory modules' cells, sense amplifiers, etc. The access portion operates on addresses and mode controls. During the access portion of a write cycle, the data is also an input to the memory modules; however, during a read cycle, the data is an output from the memory. In addition to the memory cycle time, the system logic has turnaround time between cycles which adds to the memory cycle time to make a longer system cycle time. The system's turnaround time varies considerably. The EXTEND Logic is shown in Fig. 1. A normal serial cycle operation is illustrated in Fig. 2, and a fast parallel cycle operation is shown in Fig. 3.

In Fig. 1, blocks 1, 2 and 3 are sequential logic SRLs (shift register latches) which monitor and control the different conditions encountered in extending a shortened cycle out to satisfy the memory specifications. During the EXTEND function, the system is performing its turnaround operations. Block 4 is the combinatorial logic which generates the strobes, set, and reset signals to the SRLs 1, 2 and 3.

The Address Gate latch 1 detects the activation of the Address Gate, and its output goes to the EXTEND portion of block 4.

The Edge Detect latch 2 detects if the Address Gate latch goes off and back on while the Address Gate Extend latch 3 is extending the modules' recovery time out long enough to meet specifications. If the Address Gate latch 1 does go off and back on (to start a new cycle), the Edge Detect latch 2 is set and it allows the new cycle to begin when the Address Gate Extend latch 3 is cleared at the end of the required extension at time t2 (Fig. 3).

If the Address Gate latch 1 did not do both, i.e., (1) go off and (2) go back on while the Address Gate Extend latch 3 is on, then a new cycle is not standing by to begin and the Address Gate Extend latch 3 clears without a new cycle starting as it should be. The system enters STOP state, and no more accesses are done.

The Address Gate Extend latch 3 is set at the beginning of a write cycle time t12 (Fig. 3). The Address Gate Extend output from block 3 is used in the control logic to keep the cycle time counter running and to prevent the deactivation of the Address Gate from having any effect on the control logic during the EXTEND. The output of block...