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Memory Refreshes During an Access Cycle Lock-up

IP.com Disclosure Number: IPCOM000045001D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 4 page(s) / 47K

Publishing Venue

IBM

Related People

Grimes, DW: AUTHOR [+2]

Abstract

A technique is described to prevent the destruction of memory data due to locking up in a memory cycle for a period of time exceeding the memory's maximum allowed refresh period.

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Memory Refreshes During an Access Cycle Lock-up

A technique is described to prevent the destruction of memory data due to locking up in a memory cycle for a period of time exceeding the memory's maximum allowed refresh period.

A computer system can encounter locked-up conditions during memory accesses which will prevent the memory from being refreshed. Memory refreshes cannot be performed during a memory access. Sequential logic is described that determines when a memory access has exceeded normal memory cycle time, that is, the actual memory module access has completed, but the system is locked-up. The logic takes over control, switches from access to refresh mode, performs the necessary memory refresh, and upon completion of the refresh, switches modes back to access under system control. The Locked-up Refresh Logic refreshes the dynamic memory modules to keep the data secure even though the system is locked-up in a mode which inhibits refreshes.

The logic is shown in Fig. 1, and various access and refresh conditions are illustrated in Figs. 2A-2C. Access Controls block 1 contains the logic to initiate and control memory accesses. This is in response to an Address Gate signal on line 2. The Access Controls use cycle timing signals from counter 3 on lines 4 to generate Access signals on lines 5 to the memory modules each time an Address Gate signal is received from the system.

Locked-up Refresh Controls 12 provide the necessary contention circuitry to detect lock-up conditions in the counter 3 and initiate refresh cycles via lines 6 during the lock-up as dictated by signals on the Refresh Request line 7. Counter 3 has sections A and B. Counter 3 is a Ring Counter that provides the necessary timings to control memory and refresh cycles. Should the count in section A reach a predefined time greater than the memory's cycle time with a Refresh Request pending, as evidenced by line 11, a Locked-up Refresh is executed. The Ring Counter is also used for the necessary timings for the Locked-up Refresh cycle via lines 8.

When a locked-up condition is detected in section B (Address Gate stayed on too long), the Locked-up Refresh Controls 12 are initialized into operation if Refresh Request on line 7 is active. During locked-up refreshes, block 12 inhibits block 1 from performing accesses via the Inhibit Access line 9. At the start of a Locked-up Refresh Cycle, Counter 3 is cleared via the Clear Counter line 10 from block 12 to block 3, the Locked-up Refresh Controls using the same cycle counter as the Access Control block.

A normal system memory access is illustrated in Fig. 2A. The Address Gate is activated by the system to indicate that a memory access may begin. The memory interface logic then performs the appropriate access to the memory modules. After the entire system memory cycle has completed, the Address Gate is deactivated. Memory module accesses and refreshes are mutually exclusive - only one can be performed at a time. During t...