Browse Prior Art Database

Carry Propagate for Carry Save Adder

IP.com Disclosure Number: IPCOM000045003D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Finney, DW: AUTHOR

Abstract

Propagation of the saved carry bits in a carry save adder, such as that described in the U.S. Patent 4,110,832, is accomplished in a single microcycle and the performance of all arithmetic floating point instructions is thereby improved.

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Carry Propagate for Carry Save Adder

Propagation of the saved carry bits in a carry save adder, such as that described in the U.S. Patent 4,110,832, is accomplished in a single microcycle and the performance of all arithmetic floating point instructions is thereby improved.

The data in a Carry Save Adder (CSA) is retained as a partial sum and carry bits. To obtain the correct result, the carry bits must be propagated, which would require up to 56 microcycles for double precision operands. The invention described herein will enable the propagation of the carry bits in a single microcycle.

Reference is made to the drawings. In general, the propagation may be accomplished by gating the precarry (PC) generated by the next low-order CSA bit position to the data input and adding to the sum
(S) and Carry (C) bits (Fig. 1).

PS Bit N=Sum Bit N + Carry Bit N+1 +PC Bit N+1

PC Bit N=(Sum Bit N - Carry Bit N+1) +

(Sum Bit N - PC Bit N+1) +

(Carry Bit N+1 - PC Bit N+1).

This propagates the carries in a ripple mode which involves long delays for a 60-bit CSA. Therefore, carry lookahead circuitry has been added to increase the performance of the propagation. The carry lookahead bits are generated by first determining whether or not any group of four consecutive CSA bit positions contains sum and carry bit patterns such that they would produce a carry out from the highest-order bit position in the group or whether they would propagate a carry, if any, from the next lower group (F...