Browse Prior Art Database

Computer Program Relocation and Segmentation

IP.com Disclosure Number: IPCOM000045008D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 52K

Publishing Venue

IBM

Related People

Barns, BE: AUTHOR [+3]

Abstract

A method is described for the relocation and segmentation of running computer programs within the physical memory of a computer. The relocation is done by providing each program with a logical address space consisting of multiple non-overlapping segments. Each program thus has its own virtual machine. This eliminates the need to modify instructions and data to effect the relocation. The segmentation provides protecting and sharing as well as ease of memory allocation and maximum memory usage. Segments of arbitrary and variable size, as well as a variable number of segments are utilized. Segments are shared with each user having different access capability.

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Computer Program Relocation and Segmentation

A method is described for the relocation and segmentation of running computer programs within the physical memory of a computer. The relocation is done by providing each program with a logical address space consisting of multiple non-overlapping segments. Each program thus has its own virtual machine. This eliminates the need to modify instructions and data to effect the relocation. The segmentation provides protecting and sharing as well as ease of memory allocation and maximum memory usage. Segments of arbitrary and variable size, as well as a variable number of segments are utilized. Segments are shared with each user having different access capability.

A representative system is shown in the drawing. It includes main processor 1, main memory 2, and relocation/segmentation facility 3. The system has three primary hardware portions. These are the Table Search Mechanism 4 and Base- Bounds Table Pointer (BBTP) 4a, the Base-Bounds Cache (BBC) 5, and an Adder 6 of appropriate length. Base-Bounds Value (BBV) registers 7 are also provided. The BBTP register 4a contains a physical main memory address. The BBC block 5 is a cache containing Base-Bounds values.

A Base-Bounds value has four parts: (1) Upper Logical Address (ULA), (2) Lower Logical Address (LLA), (3) Physical Starting Address (PSA), and (4) various flag bits which may indicate such things as read-only protection. Each segment is a physical piece of a program. These pieces may be (but need not be) logical divisions reflected from within the program. For example, one segment may be for instructions and another for data. Each Base-Bounds value describes one segment of a program.

When a program attempts to access an address in its logical address space, several actions occur. First, the address is fed from processor 1 to cache block 5 as a key by way of line 10. The cache has a "hit" when the key is both logically less than or equal to the ULA value for an entry and logically greater than or equal to the LLA value for the same entry.

If a "hit" occurs, cache block 5 passes the key and the PSA value of the entry to adder 6 which adds the two values. The result is used to access physical main memory, possibly dependent on the values of the bit flags for the entry.

If a "miss" (i.e., no "hit") occurs as indicated by a signal on line 11, then the table of Base-Bounds values indicated by BBTP register 4a is searched. If a "hit" occurs in the table, the entry found is loaded into cache block 5 (possibly overwriting some entry chosen by an appropriate replacement mechanism) and the key along with the PSA value are passed to adder 6, as before.

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