Browse Prior Art Database

Processor Bus Holdover for Conditional Processor Bus Branches

IP.com Disclosure Number: IPCOM000045009D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Finney, DW: AUTHOR [+3]

Abstract

A method is described for using a processor bus holdover register to do conditional branching after the data has been gated off.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Processor Bus Holdover for Conditional Processor Bus Branches

A method is described for using a processor bus holdover register to do conditional branching after the data has been gated off.

In Fig. 1, the read-only storage address register (ROSAR) is clocked every Time D. In order to branch, conditions from the processor bus (PB) must be held over from Time BC to Time D. The processor bus holdover register is clocked with the Destination Pulse (Time C) and is gated to the processor bus from just before Gate Source to PB goes away (so there will not be any glitch on the processor bus) until just after Clock ROSAR goes away (so the processor bus will be valid while the ROSAR is being clocked).

In Fig. 2, the processor bus is clocked into the processor bus holdover register 1 with the Destination Pulse. AND circuit 2 maintains valid data on the processor bus long enough for the conditional branch controls 3 to resolve the new address to be clocked into the ROSAR 4.

Fig. 3 shows several possible two-way and four-way branches. For each of the eight decodes, ROSAR bits 10 to 13 are turned on if the listed processor bus bits are on.

1

Page 2 of 2

2

[This page contains 6 pictures or other non-text objects]