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NLM ROS Bit Sets up Unique First Microcycle

IP.com Disclosure Number: IPCOM000045010D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Finney, DW: AUTHOR [+2]

Abstract

A method is described to allow the first microcycle of each instruction to be unique, thus improving the performance of a processor such as the IBM Series/1 4955 processor which always performed the same function in the first microcycle, namely, moving the Instruction Address Register (IAR) contents in the local storage to the Current Instruction Address Register (CIAR) across the processor bus.

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NLM ROS Bit Sets up Unique First Microcycle

A method is described to allow the first microcycle of each instruction to be unique, thus improving the performance of a processor such as the IBM Series/1 4955 processor which always performed the same function in the first microcycle, namely, moving the Instruction Address Register (IAR) contents in the local storage to the Current Instruction Address Register (CIAR) across the processor bus.

The drawing shows the three-microcycle pipeline overlap in this processor. The processor has a hardware IAR. Therefore, it does not tie up the local storage or the processor bus in the first microcycle. To reduce the number of microcycles in the instructions, the processor does whatever is optimal for each instruction in the first microcycle. This requires the Read-Only Storage (ROS) address of the first microcycle to be set up in the next to last microcycle (NLM),
i.e., one cycle earlier than the Series/1 processor.

The Series/1 4955 processor uses four unique decodes in the Next Address field to determine the type of last microcycle sample allowed (i.e., whether to sample for trace and/or interrupts or not) since the field was not used anyway. These same tests are required here one microcycle earlier, so an NLM ROS bit is added with three control decodes to differentiate the type of last microcycle sample allowed. Another performance aid is the ability to force more than one address into the Read-Only Storage Address Register...