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Three Bit Hardware CIAR Active Address Key

IP.com Disclosure Number: IPCOM000045011D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 52K

Publishing Venue

IBM

Related People

Herrman, BD: AUTHOR [+4]

Abstract

The IBM Series/1 processors do not retain the Address Key associated with the CIAR; they only retain the Address Key of the IAR. There are conditions when the CIAR AAK and the IAR AAK are not the same. The various expressions used in the description and drawing are listed at the end of the article.

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Three Bit Hardware CIAR Active Address Key

The IBM Series/1 processors do not retain the Address Key associated with the CIAR; they only retain the Address Key of the IAR. There are conditions when the CIAR AAK and the IAR AAK are not the same. The various expressions used in the description and drawing are listed at the end of the article.

There is a need to save the 3-bit Address Key associated with the CIAR and differentiate it from the IAR Active Address Key since they can differ if the processor enters the stop state at the first instruction of a new level. This level change can occur due to a LEX instruction or Load Level Status Block instruction or a Priority Interrupt. If, during software debug, a Stop On Address has been encountered at the first instruction of the new level, the CIAR AAK is needed to inspect the data of the CIAR.

Here, the 3-bit register is loaded during I-Phase of the processor. If an exception exists during I-Phase (i.e., Stop On Address Interrupt detected), this updating is inhibited until all exceptions have been cleared.

The data in the CAAK register is transferred from the hardware to the console LEDs through a u-code Control Function to read CAAK and LAAK. This is accomplished via the Series/1 Programmer's Console by first selecting the CIAR Key and then the AKR Key. This is a read-only function from the console.

The hardware is shown in the drawing. A "three to one" Data Selector 1 gates a 3-bit AKR key to the three inputs of the AAK register 2 during a load SAR microcode command. During the load SAR command, AAK register 2, which consists of three polarity hold latches, is loaded with a 3-bit AKR key. The three outputs of the AAK register 2 on bus 3 are gated to the address inputs of the segmentation register. Three AAK bits form the high-order part of an 8-bit segmentation register address. The LAAK register 4 also has three polarity hold latches that are loaded with the new AAK data after the execution of the load SAR microcode command. The AAK outputs feed the...