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Multiline Signature Analysis with Parity Compression

IP.com Disclosure Number: IPCOM000045036D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Gomez, RS: AUTHOR

Abstract

Signature analysis is used to compress long serial data streams into an end statement that verifies the integrity of all the data bits in a stream. It employs a feedback shift register to accomplish this purpose and is used primarily for test purposes to provide a low cost method of testing. In testing, a test point or node is monitored by placing a feedback shift register on the node and then reviewing the end statement after a long data sequence has been entered into the register. In the conventional arrangement, each node of the bit register was analyzed separately by feeding the output of an exclusive OR or to a multiplexer circuit.

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Multiline Signature Analysis with Parity Compression

Signature analysis is used to compress long serial data streams into an end statement that verifies the integrity of all the data bits in a stream. It employs a feedback shift register to accomplish this purpose and is used primarily for test purposes to provide a low cost method of testing. In testing, a test point or node is monitored by placing a feedback shift register on the node and then reviewing the end statement after a long data sequence has been entered into the register. In the conventional arrangement, each node of the bit register was analyzed separately by feeding the output of an exclusive OR or to a multiplexer circuit.

The present invention allows compression of multiple lines to feed a single analysis circuit and thus permit a single signature analysis register to test multiple modes simultaneously, greatly facilitating both conventional module and board testing using signature analysis. On chip analysis of multibit circuits also becomes feasible.

This is achieved by utilizing a shift register 10, having outputs coupled to an OR circuit 11 whose output is, in turn, coupled through an exclusive OR 12 together with the output of a parity generator 13 having a multiplicity of inputs. The output of the exclusive OR 12 is fed back to the shift register 10, as known in the art. By substituting the parity generator for the multiplexer of the prior art, the invention can now be used to verify interna...