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Logic Design Simulator using APL

IP.com Disclosure Number: IPCOM000045060D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 75K

Publishing Venue

IBM

Related People

Slishman, GR: AUTHOR

Abstract

The characteristic component of a Level Sensitive Scan Design (LSSD) is the Shift Register Latch (SRL), consisting of two D-latches, L1 and L2. Non-overlapping clocks, denoted C and B, control the L1 and L2, respectively. Since an L1 latch is never a function of L1s, and an L2 latch is never a function of L2s, adequate clock separation precludes signal races.

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Logic Design Simulator using APL

The characteristic component of a Level Sensitive Scan Design (LSSD) is the Shift Register Latch (SRL), consisting of two D-latches, L1 and L2. Non- overlapping clocks, denoted C and B, control the L1 and L2, respectively. Since an L1 latch is never a function of L1s, and an L2 latch is never a function of L2s, adequate clock separation precludes signal races.

The SRL and the absence of races suggest zero-delay simulation as a technique of second-level design and verification. Determining the exact nanosecond of input arrival at a latch is unnecessary, since the arrival cannot be too soon (D-latches) and cannot be too late (adequate clock separation).

The display hardware, VSAPL with the Extended Editor and Full Screen Manager, GRAPHPAK, and 7,000 DAV (Design and Verification) provide user- friendly tools to develop "black box" behavioral models and to transform them methodically into detailed gate-level models, mappable into the BDL/S (Basic Design Language for Structure) of EDS (Engineering Design System).

OPERATION OF 7,000 DAV. The second-level simulator resides in workspace 7,000 DAV, which runs under VSAPL with AP124 and the display hardware. The host operating system may be MVS or VM.

Having entered) LOAD 7,000 DAV, the user may notice a pause during which his display goes blank. The cause is LX which initializes AP124 and loads the programmable pattern generator.

The heart of the simulator is contained in the function SIMULATE: See Original.

The function, LSSD, is provided automatically by the simulator. LSSD makes each L2 D-latch equal to its corresponding L1. In effect, LSSD simulates what happens when the B-clock rises.

The function, PARTSLIST, is provided by the user. It names functions to be executed once during each iteration- The functions named in PARTSLIST can apply values to "receivers," or they can assign values to L1s as functions of L2s and receivers. In effect, the functions invoked by PARTSLIST simulate what happens when the C-clock rises.

To build the function, LSSD, and to allocate tracing variables, the simulator uses a function named SRLSLIST. As the name implies, SRLSLIST lists the SRLs in the design and specifies the format of the trace. An SRL named in the list will not be traced if the character 'A' precedes its name. The SRL name 'delta' serves to reserve a space between lines of the timing diagram. Each SRL is a global variable pre-allocated as a 2 element vector or an Mx2 matrix simulating an M-bit register.

Having the two functions, PARTSLIST and SRLSLIST, the user enters S(IMULATE) TIME, where TIME is the number of B-clocks to be simulated....