Browse Prior Art Database

High Performance Lateral Bipolar Devices

IP.com Disclosure Number: IPCOM000045076D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Abbas, SA: AUTHOR [+2]

Abstract

A self aligned metallization process for lateral bipolar devices involves providing a silicon body having dielectrically isolated silicon regions 8 therein and then forming a first insulating layer on the major surface of the silicon body having the isolated regions 10. The first insulating layer is removed in areas designated to contain the high performance bipolar devices. The base region 12 is formed in these areas. A silicon dioxide layer (not shown) is formed to cover these areas. A layer of first polycrystalline silicon (not shown) is formed thereover. Openings are made in the first polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

High Performance Lateral Bipolar Devices

A self aligned metallization process for lateral bipolar devices involves providing a silicon body having dielectrically isolated silicon regions 8 therein and then forming a first insulating layer on the major surface of the silicon body having the isolated regions 10. The first insulating layer is removed in areas designated to contain the high performance bipolar devices. The base region 12 is formed in these areas. A silicon dioxide layer (not shown) is formed to cover these areas. A layer of first polycrystalline silicon (not shown) is formed thereover. Openings are made in the first polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. An insulating layer composed of a layer of silicon dioxide 16 and a layer of silicon nitride 14 is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. A second polycrystalline conformal layer 18 is deposited over the insulating layer 14, 16. Reactive ion etching of this second polycrystalline silicon layer substantially removes the horizontal layer and provides a narrow dimensioned pattern of regions on the major surface of the silicon body. The polycrystalline silicon layer pattern 18 is subjected to a thermal oxidation ambient to oxidize the surface of the polycrystalline silicon to a silicon dioxide layer 20. This results in the formation of studs 21. The oxidation need not consume the whole layer, as shown in Figs 1 and 2. A pyrocatechol etchant is now utilized to remove the first polycrystalline silicon layer.

Openings are made in the silicon dioxide layer covering the regions designated to be the emitter and collector of the lateral transistor.

Ion implantation or diffusion of the appropriate conductivity imparting impurity and heating forms the emitter 22 and collector 24 regions.

Typically, the stud...