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Polysilicon Base Transistor Structure with Improved Characteristics

IP.com Disclosure Number: IPCOM000045082D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Antipov, I: AUTHOR [+2]

Abstract

A method is disclosed to realize a polysilicon-base transistor structure which is shown in its essential form in Fig. 4 just prior to the etching of holes for base and collector metal contacts. In this structure, the base/collector junction is away from the N+ subcollector by about 0.2 0.3 Mum in both the extrinsic and intrinsic base regions. This results in an appreciable reduction in the base/collector capacitance (without any increase in the thickness of the N- region below the intrinsic base region). The disclosed method also facilitates further appreciable reduction in the base/collector (and collector-isolation) capacitance by allowing reduction in the (horizontal) width dimension of the base area.

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Polysilicon Base Transistor Structure with Improved Characteristics

A method is disclosed to realize a polysilicon-base transistor structure which is shown in its essential form in Fig. 4 just prior to the etching of holes for base and collector metal contacts. In this structure, the base/collector junction is away from the N+ subcollector by about 0.2 0.3 Mum in both the extrinsic and intrinsic base regions. This results in an appreciable reduction in the base/collector capacitance (without any increase in the thickness of the N- region below the intrinsic base region). The disclosed method also facilitates further appreciable reduction in the base/collector (and collector-isolation) capacitance by allowing reduction in the (horizontal) width dimension of the base area. Furthermore, the disclosed method guarantees a good linkage between the extrinsic and intrinsic base regions, the base resistance also being a little lower as a by-product.

A preferred implementation of the proposed method is the following:

1. Starting with a P- substrate, complete the processing through the formation of N+ collector reach-through following conventional processing.

2. Using masking, form a P region, identified as region 8 in Fig. 1, preferably through ion implantation across a screen oxide. Obtain a layer 9 of about 1,800 A SiO(2), preferably through chemical vapor deposition (CVD). The transistor structure at this stage is depicted in Fig. 1. N regions 2 and 7 are the subcollector and collector reach-through regions, respectively. N- layer 4 is the epitaxially formed silicon region whose thickness is designed so as to obtain about 0.2-0.3 Mum N region between the P base and N+ subcollector of the final transistor structure. Region 6 denotes the recessed SiO(2). It is specifically to be noted that the same masking and ion implant operations which are used to form P regions 8 of the transistors can also be simultaneously employed to form P resistors elsewhere on the chips.

3. Using masking etch "base" windows in SiO(2)9, deposit about 3,500 Angstrom polysilicon 10, form about 1,000 A SiO(2) 12 above polysilicon 10, ion implant, e.g., boron in the polysilicon 10, form patterns in the composite of SiO(2) and polysilicon 10, optionally form a layer of SiO(2) form about 1,600 Angstrom layer 14 of Si(3)N(4) and then pattern the composite Si(3)N(4) 14, the optional SiO(2) 12 and polysilicon 10 to obtain the structure of Fig. 2. 4. Form about 3,500 Angstrom thick insulation sidewall 16 at the side of the composite just patterned. In Fig. 3, this sidewall is shown to be consisting of a composite of about 500 Angstrom SiO(2), about 800 A Si(3) N(4) and about 2,200 A SiO(2). 5. After formation of insulation sidewall 16, etch exposed silicon to a depth slightly below the depth of P region 8, as indicated at 18 in Fig. 3. A selective RIE (reactive ion etchant), e.g., SF(6)/C1(2), is preferred for this...