Browse Prior Art Database

Versatile Programmable Logic Array

IP.com Disclosure Number: IPCOM000045087D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 4 page(s) / 43K

Publishing Venue

IBM

Related People

Langmaid, RN: AUTHOR

Abstract

This article concerns a programmable logic array capable of executing various functions. The array features the use of a grid of two sets of data lines with a specialized logic circuit at each of the intersections of the grid. The description will refer to vertical and horizontal sets.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 43% of the total text.

Page 1 of 4

Versatile Programmable Logic Array

This article concerns a programmable logic array capable of executing various functions. The array features the use of a grid of two sets of data lines with a specialized logic circuit at each of the intersections of the grid. The description will refer to vertical and horizontal sets.

In one form, as shown in Fig. 1, the grid includes horizontal data lines 2 for receiving a data input and vertical data lines 3 for providing a data output. In the region of each intersection 4, the vertical lines 3 are shown to include specialized logic circuits. Particularly included are a data latch 5, capable of being set from outside the device, arranged to drive an AND gate 6, itself configured to drive an Exclusive (E) OR gate 7. A second input to AND gate 6 is driven by the horizontal data line. A second input to EOR gate 7 is driven by the output on the vertical data line coming from the previous EOR gate. The uppermost EOR gate is driven by the output of an AND gate and a fixed logic zero.

In operation, if the output of AND gate 7 is a logic 1, then EOR gate 7 will act as an INVERT block; while if the output of the AND gate 6 is a logic 0, then the EOR gate will act as an IDENTITY block. The output of AND gate 6 is a logic 1 only when latch 5 provides a logic 1 and the associated horizontal data line 2 provides a logic one. Thus the final output of the vertical data line 3 depends on how many EOR gates 7 on the line are acting as INVERT blocks. If an even number are acting as INVERT blocks,, then the output will be a logic O. If an odd number are acting as INVERT blocks then the output will be a logic 1.

With regard to the convention of the examples, it should be noted that the content of the latches 5 is considered as a matrix of 1's and 0's, horizontal data lines 2 receive a vector of 1's and 0's and vertical data lines 3 deliver a vector of 1's and 0's. An illustration of this convention is given in the following example: a b c d

1 1 1 1 1

0 0 1 0 1

INPUT 1==> 0 0 1 1 1 0 1 1 1

GIVES

1 0 1 1.

The output from column a is a logic 1 because of the single inversion at the top of the column. The output from column b is a logic 0 because of the double inversion at the top and bottom of the column. The output of column c is a logic 1 because of a triple inversion at the locations where the logic 1's match in the latches in the column and the input data. The output of column d is also a logic 1 because of a triple inversion, but the output of this column will depend only on whether the number of logic 1's in the input vector is odd or even.

The physical array may be used to perform a variety of functions. For example, the array may be used for code conversions. To illustrate, the following fill will convert binary to Gray code: 1 1 1 0 0

1

Page 2 of 4

0 0 1 1 0

INPUT 1==> 0 0 1 1

1 0 0 0 1

GIVES

1 1 1 0.

The array may also be used to invert code conversion. The next example shows a data fill that will convert...