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Redundancy with Switching Transistors

IP.com Disclosure Number: IPCOM000045091D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Malaviya, SD: AUTHOR

Abstract

The redundancy technique is based upon the availability of a transistor which can be electrically pulsed during the wafer test to create a permanent short between the emitter and the collector, e.g. by outdiffusion of a specially implanted layer of phosphorus near the base. The base to collector and base to emitter junction remains unimpaired by the pulsing.

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Redundancy with Switching Transistors

The redundancy technique is based upon the availability of a transistor which can be electrically pulsed during the wafer test to create a permanent short between the emitter and the collector, e.g. by outdiffusion of a specially implanted layer of phosphorus near the base. The base to collector and base to emitter junction remains unimpaired by the pulsing.

Referring to the figure, the address lines are shown as A1, A1, A2, etc. Both true and complement lines are used as usual. A TTL (transistor-transistor logic) type of decoder is shown here for illustration of the concept but the scheme is equally applicable to other types of decoders, such as a current switch.

In a normal line, either the true or the complement address is permanently wired to the emitter. Instead of two emitters shown in the figure, only one is used in real products, with the via missing either from the true or the complement line.

Q refers to normal transistors, while T refers to the special transistors which can be pulsed to create permanent link-up between the base and the collector (very small or zero punch-through voltage after pulsing).

The additional devices T1, Q1, R2 and R3 needed in the normal lines are shown to the left of the address line A1.

Redundancy is exercised as follows:

1. Stop the electrical tester at the faulty bit address. Suppose the address A1 is up at this time; its complement will then be low.

2. The redundancy pad shown at the upper right hand corner of the figure is pulsed several times with short duration (e.g., 10 micro-seconds) low duty cycle negative pulses. The pad is normally held at a positive voltage due to the resistor R1. The output of this pad is connected to the cathodes of the Schottky diodes, as shown by the cross and circle symbols.

3. Of all the decoder outputs, only one output is up - that of the faulty line. Hence only T1 will be strongly pulsed by the tester pulses. Heat generated by the pulsing will short the emitter of T1 to its collector. This will happen only to the faulty line. At the end...