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# LSSD Testable Ring Oscillator

IP.com Disclosure Number: IPCOM000045106D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 66K

IBM

## Related People

Schoenike, RL: AUTHOR

## Abstract

In order to obtain high testability in logic built on large-scale integrated (LSI) circuits, designers follow level sensitive scan design (LSSD) ground rules in the design cycle, such as are described in U.S. Patent 3,761,695. One of these ground rules specifies that there can be no combinational logic feedback. This ground rule provides a problem when designing ring oscillators. Ring oscillators are used to get a quick measurement of the propagation delay of a single-gate type.

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LSSD Testable Ring Oscillator

In order to obtain high testability in logic built on large-scale integrated (LSI) circuits, designers follow level sensitive scan design (LSSD) ground rules in the design cycle, such as are described in U.S. Patent 3,761,695. One of these ground rules specifies that there can be no combinational logic feedback. This ground rule provides a problem when designing ring oscillators. Ring oscillators are used to get a quick measurement of the propagation delay of a single-gate type.

A typical ring oscillator design is shown in Fig. 1. The odd number of inverters ensures that the chain will oscillate. The ODRO gate is simply an off-chip driver so the oscillation frequency can be measured. Then the period of the measured frequency is calculated, divided by two times the number of inverters in the chain, and the result is the average propagation delay of a single inverter.

This prior-art design has three problems: 1. The ring is usually physically laid out much like the logic diagram of Fig. 1, with the string of inverters in a line and

the last one driving a very long line back to the first

inverter. Thus the propagation delay of the last inverter

will be very long compared to the others, skewing the

measurement. 2. Since combinational logic feeds back on itself, the ring is not LSSD compatible and is therefore statically untestable.

While the untestability of this logic may not be significant,

it does mean that it must be divorced from the other logic on

the chip which is LSSD testable, and this creates design

management problems. 3. If it is desired to test the propagation delay of a different circuit (say, a D), then another ring must be constructed.

The ring oscillator design shown in Fig. 2 provides for more accurate gate delay measurements, is LSSD compatible, and tests various circuits with a single ring. The shift register latch, SRL1, which is a single input shift register latch, is inserted in the ring to make the logic LSSD compatible. Since shift register latches (SRLs) are flush throug...