Browse Prior Art Database

Multifunction Circuit Cell

IP.com Disclosure Number: IPCOM000045108D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Bansal, JP: AUTHOR

Abstract

A multifunction circuit cell is disclosed for a master slice , technology which can be selectively formed into a variety of elementary logic functions.

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Multifunction Circuit Cell

A multifunction circuit cell is disclosed for a master slice , technology which can be selectively formed into a variety of elementary logic functions.

A basic layout of diffusions and polycrystalline silicon gate electrodes for the multifunction circuit cell is shown in Fig. 1. The diffusions D1 through D6 are N- type diffusions, for example, which are diffused or ion implanted into a P-type silicon substrate in the pattern shown in Fig. 1. After suitable gate and field oxidations, the polycrystalline silicon gate electrodes G1 through G5 are deposited, as shown in Fig. 1. Semiconductor wafers can be stockpiled after having been fabricated to the stage represented by Fig. 1. When a particular complex logic function is to be embodied from the interconnection of a large number of elementary logic functions, those elementary logic functions can be selectively formed from any one of the multifunction circuit cells of Fig. 1 by suitable patterns of metallization interconnecting lines and interlayer contacts. The following two examples will illustrate the flexibility of the multifunction circuit cell layout.

Fig. 2 illustrates the metallized interconnection lines and metallized contacts required to embody a four-input NOR elementary logic function, such as is shown in the schematic diagram of Fig. 3. Three metallized lines are laid down, line 1 is connected to the positive VDD potential, line 3 is connected to ground potential, and line 6 connects several of the diffusions. Line 1 is connected through the metallized contact 2 to the diffusion D1 which will serve as the drain electrode of the load device L1. The ground metallization 3 is connected through a metal contact 4 to the diffusion D3 and through a metal contact 5 to the diffusion D5. Diffusion D3 serves as the common source diffusion for active devices A1 and A2 (Fig 3) and diffusion D5 serves as the common source diffusion for active devices A3 and A4. The metallized line 6 is connected by means of the metal contact 7 to the polycrystalline silicon gate electrode G1, which serves as the output electrode OUT for the circuit. Metallized line 6 is connected by means of the metallized contact 8 to the diffusion D2, which serves as the source diffusion for the load device L1 and the drain diffusion for the active device A1. Metallized line 6 is connected by means of the metal contact 9 to diffusion D4, which serves as the drain for the active FET devices A2 and A3. The metallized line 6 is connected by m...