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Clock Generator Circuit

IP.com Disclosure Number: IPCOM000045110D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 59K

Publishing Venue

IBM

Related People

Puri, YK: AUTHOR [+2]

Abstract

Where several semiconductor chips must each generate several clock waveforms on their respective chips from a commonly distributed, free running clock waveform, synchronization must be established where one chip, considered the master chip, develops a synchronizing signal which is distributed to all of the other chips along with the commonly distributed free running clock waveform, so that all chip clock generators generate corresponding clock waveforms in unison.

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Clock Generator Circuit

Where several semiconductor chips must each generate several clock waveforms on their respective chips from a commonly distributed, free running clock waveform, synchronization must be established where one chip, considered the master chip, develops a synchronizing signal which is distributed to all of the other chips along with the commonly distributed free running clock waveform, so that all chip clock generators generate corresponding clock waveforms in unison.

An additional problem confronted in designing a clock generator circuit is that latches are ordinarily used to define the several states of the clock generator circuit. Where N latches are used, theoretically as many as 2/N/ states can be defined. Where less than 2/N/ states are necessary for a particular clock generator circuit, those states which are not utilized in the clock generation circuit can pose a problem of becoming a trap state when the circuit is turned on. This occurs because the state of a particular latch when it is turned on is arbitrary, and if the combination of latch states at the initial turn on is one of the trap states, some mechanism must be provided to insure that the circuit will default to one of the utilized states.

A still further problem which must be addressed in clock generator circuits is the overall delay time between the input of the clock waveform transition and the output of the generated waveforms. If a significant delay occurs, then skewing can take place between the generated clock waveforms and external timed operations which derive their timing from the input clock waveform.

Fig. 1 is the logic block diagram for the clock generator circuit which appears on each of the several semiconductor chips. On the master chip, the input sync waveform line is connected to ground and disabled. On all other semiconductor chips, the input sync waveform line is connected to the output sync signal from the circuit on the master chip. In this manner, synchronization of the clock generator circuits on all of the slave chips is achieved from the output sync signal generated on the master chip.

Fig. 2 illustrates the state diagram for the A latch and the B latch on any master or slave chip. The A latch and the B latch are connected with their outputs input to the NOR circuit 1, whose output is in turn connected to the input of the A latch. The clock input to the latch A and the latch B is connected to the input free running clock waveform CLK. As seen in the state diagram of Fig. 2, if, when the chip is turned on, its state is AB equals 00, 01 or 10, these are non- trapping, utilized states and no problem is incurred in starting out in a trapped state. If AB equals 11, the logic sta...