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Store Buffer

IP.com Disclosure Number: IPCOM000045119D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 4 page(s) / 43K

Publishing Venue


Related People

Fletcher, RP: AUTHOR [+2]


This article describes a line store buffer for receiving the store transfers to the main storage of a uniprocessor (UP) or multiprocessor (MP) system to improve the performance of the system.

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Store Buffer

This article describes a line store buffer for receiving the store transfers to the main storage of a uniprocessor (UP) or multiprocessor (MP) system to improve the performance of the system.

A store-thru (ST) cache enables its CPU to write all stores directly into main storage (MS). This causes MS to have a high utilization. Consequently, the use of a ST cache results in serious performance degradation because of contention for MS by the CPU(s) and channels which increases as the number of CPUs increase in a MP system.

The store-in cache design is effective in reducing the utilization of MS in MP systems. However, store-in caches introduce the increased complexity of cross- interrogation and resulting forced castouts.

A small and specialized store buffer (SB) may be positioned logically between each CPU ST cache and MS. The SB could be physically packaged with either the storage controls or with the MS basic storage modules (BSMs). Fig. 1 is a schematic of a MP including the SB.

The SB exploits the program phenomenon called locality of reference to reduce the number of times MS is made busy to accomplish a store. Locality of reference means that a storage reference to a given address will soon be followed by other references to that same address or to a closely neighboring address.

In a ST cache, every store is presented to the storage control before it is written into MS, and each store may be written into the cache by its CPU if and only if the relevant cache line is already in the cache.

There are important differences to be noted in comparing the conventional ST cache to the SB. The ST has a similarity to the cache but is in many respects an inverse. These differences are: 1. The cache holds data which has been fetched and which is intended to go into the CPU. The SB holds data which has

been stored and which is intended to go into the MS. 2. The cache is large (256 to 512 cache lines), while the ST is small (4 to 8 cache lines). 3. The cache is usually set associative, while the SB is fully associative. 4. The cache always contains full cache lines, while the SB usually contains partial cache lines.

The SB is addressed by means of a set of SB address registers (SBARs). It is by virtue of simultaneous comparison of a storage address with these SBARs that the SB is fully associative. A valid address in the SBAR means that stores to that cache line are being accumulated in the SB. Data integrity is maintained by prohibiting that cache line from being fetched directly from MS.

Each position in which parts of a cache line may be stored is


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referred to as a store buffer "slot". Fig. 2 provides a detailed view of the content of one SB slot. The number of slots in the SB is the number of cache lines for which the SB is accumulating stores.

If the SB consists of four slots, then stores to any of the four lines indicated by the SBARs are made in the SB. Each SBAR corresponds to a specific SB slot. Each byte i...