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Fault Tolerant Serial Shift Arrangement

IP.com Disclosure Number: IPCOM000045152D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 9 page(s) / 63K

Publishing Venue

IBM

Related People

Tsui, F: AUTHOR

Abstract

A fault tolerant serial shift arrangement is described, which enhances the probability of a serial shift arrangement remaining usable even in the presence of faults. Redundancies are incorporated in the serial shift arrangement, so that latches will be joined to form bidirectional shiftable chains, and that such a change will be subdivided in segments to be joined by gated connections in order to provide switchable alternative configurations. The bidirectional shiftability renders a shiftable chain testable and diagnosable for faults, while the configurability increases the probability of a serial shift arrangement being usable after faults are detected and located.

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Fault Tolerant Serial Shift Arrangement

A fault tolerant serial shift arrangement is described, which enhances the probability of a serial shift arrangement remaining usable even in the presence of faults. Redundancies are incorporated in the serial shift arrangement, so that latches will be joined to form bidirectional shiftable chains, and that such a change will be subdivided in segments to be joined by gated connections in order to provide switchable alternative configurations. The bidirectional shiftability renders a shiftable chain testable and diagnosable for faults, while the configurability increases the probability of a serial shift arrangement being usable after faults are detected and located. The technique requires a moderate amount of additional circuitry and I/O expenditure, and is applicable to all semiconductor, Josephson, and other LSI circuit technologies.

The serial shift arrangement, which can be used independently or in conjunction with the LSSD (level sensitive scan design) is a scheme for furnishing, under the constraints of I/O limitation, a means for testing and diagnosing LSI logic circuitry of the chip, module, and system levels. The arrangement consists in connecting all of the register elements (latches) on a chip, in a module, and in the whole system into one or more shiftable chains, and utilizing these in a scan mode of operation under appropriate controls. In this mode, contents, as desired will first be shifted into the latches. Then, the logic circuits (combinatorial networks) will be run through one or more timing cycles, at the end of which the logic circuit output will be stored into the latches again. Finally, the contents of the latches will be shifted out so as to allow the results to be analyzed. The serial shift feature offers testability of LSI logic at the cost of using only a small number of I/O's and a moderate amount of additional circuitry. However, there is a fundamental weakness in the serial shift arrangement because the feature is critically dependent on the perfect functioning of the shiftable chains. Any single fault in a shift register chain renders the whole chain unusable. Although there have been partial remedies proposed for this problem, the improvement offered are relatively limited, in that a single fault in the connections in a chain still renders that chain totally unusable.

The fault tolerant serial shift arrangement described here is fully testable and diagnosable and, in the presence of faults in its shift connections, will still remain completely usable in most cases. Principle of Scheme for Fault Tolerant Serial Shift Arrangement

This scheme relies mainly on the incorporation and utilization of redundancies. The shift register chains become fault tolerant by incorporating and utilizing redundancies in their shift connections. This scheme will not incorporate any redundancy in the ultimate object of the tests, i.e., in the main body of the circuitry proper to be...