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Measurement of Execution Unit Cycles Per Instruction VIA Alternating Recording

IP.com Disclosure Number: IPCOM000045158D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 79K

Publishing Venue

IBM

Related People

Hennet, PP: AUTHOR [+4]

Abstract

Measurement of a central processing unit can provide the data necessary to determine the average number of execution (E)-unit machine cycles per instruction, for each instruction type. Depending on the environment to be measured, this can be accomplished in several ways.

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Measurement of Execution Unit Cycles Per Instruction VIA Alternating Recording

Measurement of a central processing unit can provide the data necessary to determine the average number of execution (E)-unit machine cycles per instruction, for each instruction type. Depending on the environment to be measured, this can be accomplished in several ways.

For benchmarks in a laboratory, an Accumulative Distribution Decoder (ADD- 1) type counting unit (1) can be connected to the CPU and two successive measurements of the same benchmark can be performed. The first measurement counts the number of instructions of each type. The second measurement counts the number of E-unit busy cycles for each type of instruction. Dividing the second set by the first set results in the average number of B-unit busy cycles per instruction (for each instruction type). This type of measurement requires a reproducible benchmark and one ADD-1 counting unit.

Another way to produce the same result is to connect two ADD-1 units to a CPU and then run benchmarks or any non-reproducible environment. This setup requires the synchronization of the two ADD-1 units and the ability to bring the required CPU signals to both ADD-1 units simultaneously.

For measurements on operational systems, the first method is not feasible and the second requires two ADD-1 units to be connected to the CPU and synchronized to a recording media. A method was developed to accomplish the same result by using only one ADD-1 unit for such measurements. This was achieved by connecting an ADD-1 unit so that it recorded the instruction count for one interval of time and the E-unit busy cycles during the next interval in succession. By applying statistical tests to the samples, it can be determined if enough samples have been taken to assure a high confidence in the resulting average number of cycles per instruction estimates. It has been shown that, in practice, this methodology can accurately estimate the cycles per instruction for over 98 percent of all E-unit busy time.

In Fig. 1, CPU signals are brought to a 128 Totalizer (2), which is a hardware monitor that contains 128 counters for counting and timing signals and an ADD-1 unit. The ADD-1 unit increments the logical counter, decoded by the 8 bits presented to it, every time a strobe is applied to its input. Logic is used to determine the correct strobes required to count instruction frequency and instruction Eunit busy time. The 128 Totalizer con...