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Testing Flexible Disk Controllers with Signature Analysis

IP.com Disclosure Number: IPCOM000045164D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Rodriguez, AA: AUTHOR [+3]

Abstract

Flexible disk controllers are usually a part of a feedback organization, such as a phase-locked loop together with the flexible disk drive unit. Since electrical/mechanical equipment, such as flexible disk drive units, are difficult to synchronize to signature analysis test equipment with the precision needed for signature analysis testing, it has been difficult to utilize that technique for verifying correct operation of the controller. This article discloses the use of s simulator to simulate the flexible disk drive and thus eliminate the asynchronous relationship between the flexible disk controller, the disk drive and the signature analysis CPU.

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Testing Flexible Disk Controllers with Signature Analysis

Flexible disk controllers are usually a part of a feedback organization, such as a phase-locked loop together with the flexible disk drive unit. Since electrical/mechanical equipment, such as flexible disk drive units, are difficult to synchronize to signature analysis test equipment with the precision needed for signature analysis testing, it has been difficult to utilize that technique for verifying correct operation of the controller. This article discloses the use of s simulator to simulate the flexible disk drive and thus eliminate the asynchronous relationship between the flexible disk controller, the disk drive and the signature analysis CPU. In order to stress test the control unit, the simulator is provided with the capability of simulating maximum drive speed fluctuations and the consequent phase and frequency fluctuations of the read data to the limits of the response characteristics of phase locked loop data separators.

The simulator operates by serializing encoded byte parallel data and converting it to the necessary pulse stream which would be seen by a controller during a read operation. This encoded data stream, along with the CPU- generated read/write commands, enables the implementation of a complete test on the controller. The simulator is shown in a block diagram in Fig. 1, and operates in the following manner: The first byte of encoded data is written out to the transparent latch 10 under control of the signature analysis test unit CPU; also, reset to the simulator is removed. The byte is transferred from the transparent latch 10 to the parallel-in, serial-out (PISO) shift register 11 and thereafter is shifted out. However, before the first byte is completely shifted out, a direct memory access (DMA) request is issued. The next byte and all subsequent bytes are loaded to the transparent latch under DMA control with one DMA request for each byte loaded to the transparent latch. This sequence continues until the end of transfer. The data from the parallel-in, serial-out shi...