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Signature Analysis Testing of On Card ROS

IP.com Disclosure Number: IPCOM000045168D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Davis, GT: AUTHOR [+4]

Abstract

This article describes a technique for providing a signature analysis test of on-card ROS (read-only storage) by first degating the ROS to permit the on-card microprocessor to fetch op codes from a functional test unit and place them at the beginning of RAM (random-access memory) space. The ROS is then enabled and cycled through a signature analysis verification controlled by the op codes stored in RAM.

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Signature Analysis Testing of On Card ROS

This article describes a technique for providing a signature analysis test of on-card ROS (read-only storage) by first degating the ROS to permit the on-card microprocessor to fetch op codes from a functional test unit and place them at the beginning of RAM (random-access memory) space. The ROS is then enabled and cycled through a signature analysis verification controlled by the op codes stored in RAM.

A signature analysis functional tester (SAFT) is designed to provide test sequencers to exercise a card under test (CUT) through a special personality card (PC) which provides an interface between the SAFT device and the card under test. However, the testing of on-card ROS elements requires a special strategy. In the technique described here, the test is performed by reading each byte of a ROS module onto the data bus and taking signatures on the data bus with signature analysis. This is done by providing a test point on the product card which can be controlled by the microprocessor on that card via an I/O port in the tester (or on the card under test) which degates the ROS memory on that card when activated.

Fig. 1 shows such a test point 10 connected to enable or disable the ROS module 11 through ROS port 12. A test microcode port 13 is simultaneously enabled, and since both of these ports occupy the same address, 0000 to 7FFF, the test microcode port is made accessible to microprocessor 14. The first part of the test mi...