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Improved Resolution Data Strobe Increases System Performance

IP.com Disclosure Number: IPCOM000045176D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 34K

Publishing Venue

IBM

Related People

Grimes, DW: AUTHOR [+4]

Abstract

Data Strobe skew is sometimes excessive, causing a degradation in system performance. This is resolved by the technique described here.

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Improved Resolution Data Strobe Increases System Performance

Data Strobe skew is sometimes excessive, causing a degradation in system performance. This is resolved by the technique described here.

A computer system frequently uses a Memory Data Strobe (MDS) as an acknowledgment signal to the system logic from the memory interface, indicating that a memory access is finished. The trailing edge of the Memory Data Strobe is the transition which the system logic triggers on; thus, this description will reference only the trailing edge when the Memory Data Strobe makes a transition from on to off.

In a typical system, the ideal condition of the Memory Data Strobe is that it always turns off within a set 50 ns window between two clock transitions, for example, the 50 ns window from T1 to T2 as indicated at the top of Fig. 3. With MDS always turning off prior to T2, the system logic will latch MDSs off state at time T2. A skewed MDS may be generated in Fig. 1 which includes a Cycle (or ring) Counter 1, a Decoder A block 2, and an Off-Chip Driver 3. Stage delays are encountered in the combinatorial logic of the Decoder A block 2 into which modal Gates and Inhibit signals are also inputs by way of lines 4 and 5. Block 2 output is nominally at 24 ns after Tl clock time (Fig. 3), but due to technology manufacturing process variations, power supply variations, and environmental fluctuations, the exact time at which it occurs will skew early or late relative to nominal, as illustrated by the transitions on each side of the 24 ns transition.

More delay and associated wider skew are added on as the signal traverses to the chip output. At this poi d, the nominal time for the skewed MDS is 36 ns with the fast and late skewed times of 18 ns and 54 ns, respectively. Note that the system clock at T2 time occurred prior to the late skewed MDS. Sensing of the MDS by the system would not occur until T4 time, which is 100 ns excess system cycle time.

The synchronized MDS is illustrated in Fig. 2. It includes Cycle Counte...