Browse Prior Art Database

Bus Attachable Storage Interface

IP.com Disclosure Number: IPCOM000045179D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

Martinez, PL: AUTHOR

Abstract

An efficient interface is provided between a Bus and Main Storage. The main features are: 1. Storage Relocation Translator 2. Error Correcting Code (ECC) 3. Parity Checking and Generating from and to Bus 4. Read Modify Write Function for one-byte transfers 5. Main Storage Refresh and controls 6. Packaged in one very large-scale integration (VLSI) logic chip.

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Bus Attachable Storage Interface

An efficient interface is provided between a Bus and Main Storage. The main features are: 1. Storage Relocation Translator 2. Error Correcting Code (ECC) 3. Parity Checking and Generating from and to Bus 4. Read Modify Write Function for one-byte transfers 5. Main Storage Refresh and controls 6. Packaged in one very large-scale integration (VLSI) logic chip.

The hardware and functions are illustrated in Figs. 1 and 2. The primary blocks of interest are: In Fig. 1

Bus 1: (la in Fig. 2) The common channel for interfacing the

microprocessor, Device Functional Units (DFUs), etc. This

bus is architected, and a set of signal lines is defined.

Segmentation Register Addressing 2: This block decides

whether the Seg Regs 3 will be addressed for Relocation

Translation or whether the Seg Regs are going to be written

into or read from. The addressing scheme is different for

both cases.

Segmentation Registers 3: This is a 256 x 16 RAM

(Random-access Memory) macro within the logic chip.

The data contained in the Seg Regs along with the 11

low-order Address Bus Bits comprise a 24-bit physical

address. Reference is made to U.S. Patent 4,042,911

for details of a Relocation Translator used in the system.

Selector 4: Gates the Address Bus when the Relocation

Translator is not enabled. Gates Seg Regs data when the

Translator is enabled. The Relocation Translator is

enabled and disabled by IBM Series/1 Enable and Disable

instructions, respectively.

Address Buffer 5: Latches the selected address and feeds back

to the selector to maintain the selected address active.

Storage Interface 6: Formats the physical address into row

and column selects and controls associated with the main

memory modules.

Address Controls and Checks 7: Provides timings and controls

for the various logic stages. Checks for invalid conditions

in using the Relocation Translator and Invalid Storage

Addresses (ISA) associated with the physical address

generated.

Main Storage 8: Up to 512KB of dynamic storage is supported

with this Storage Interface Chip.

In Fig. 2:

Parity Check 9: Odd parity is checked on the data coming

from the Bus.

Data Gating Selector 10: Gates data from the Bus and, along

1

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with the Data Buffer 11, maintains the data active internal

to the Storage Interface Chip.

Data Buffer 11: Latches data from the Bus on Stor...