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Divided by 12 for Controlling Data Wrap

IP.com Disclosure Number: IPCOM000045180D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Baker, RG: AUTHOR [+3]

Abstract

Conventional flexible diskette controllers, such as the NEC type 765, ccept standard "FM" data during a data window that is low during the lock time of the bit cell and high during the data time. The diagnostic wrap function takes parallel data from the main processor and converts it to FM format serial clock and data bits. Referring to Fig. 1, a diagnostic wrap function circuit is shown which uses a divided by 12 counter to serialize the data and provide the data window. The data wrap occurs when the attachment is placed into a diagnostic mode by setting the diagnostic mode line at the output of data register 10. Then parallel data is provided at the output of data register 10 as 2 clock bits and 2 data bits representing 2 bit cells. This is done every 7 microseconds.

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Divided by 12 for Controlling Data Wrap

Conventional flexible diskette controllers, such as the NEC type 765, ccept standard "FM" data during a data window that is low during the lock time of the bit cell and high during the data time. The diagnostic wrap function takes parallel data from the main processor and converts it to FM format serial clock and data bits. Referring to Fig. 1, a diagnostic wrap function circuit is shown which uses a divided by 12 counter to serialize the data and provide the data window. The data wrap occurs when the attachment is placed into a diagnostic mode by setting the diagnostic mode line at the output of data register 10. Then parallel data is provided at the output of data register 10 as 2 clock bits and 2 data bits representing 2 bit cells. This is done every 7 microseconds. On the trailing edge of loading data register 10, run latch 12 is set. The set/reset latch 14 synchronizes the enabling of divided by 12 counter the 2 MHz clock.

The Q0 and Q3 outputs of divided by 12 counter 16 are applied to the S1 and S0 selecting inputs of multiplexer 18. Referring to Fig. 2, at time T1, both Q0 and Q3 are low, thereby causing the CLK0 input to multiplexer 18 to be selected as the file data signal at the output of multiplexer 18. The Q1 output from counter 16 and the 2MHz clock signal are both provided to AND gate 20, the output of which enables multiplexer 18. The Q3 output of counter 16 is the data window signal. Thus, time T1 may be co...