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Constants Generator for a VLSI Microprocessor

IP.com Disclosure Number: IPCOM000045185D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 4 page(s) / 66K

Publishing Venue

IBM

Related People

Landa, RE: AUTHOR [+2]

Abstract

Logic circuits are minimized to reduce chip size while still maintaining function/performance so that the chip meets fabrication specifications of complementary field-effect transistor (CFET) technology, for example.

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Constants Generator for a VLSI Microprocessor

Logic circuits are minimized to reduce chip size while still maintaining function/performance so that the chip meets fabrication specifications of complementary field-effect transistor (CFET) technology, for example.

An objective in every logic design is to minimize the amount of logic circuits needed to perform a given function. This is especially important when designing in very large-scale integration (VLSI), where one is trying to obtain the maximum number of functions in the least amount of space, that is, in a single logic chip. The more the logic is minimized, the smaller the logic chip will be, which means that more chips can be fabricated per wafer. Thus, the price per chip decreases.

A method is described for reducing chip area by minimizing the amount of logic circuits needed in the control section of the microprocessor. This is accomplished by incorporating a "constants generator".

For background, a microprocessor control section is first discussed (Fig. 1).

It is assumed that a programmable logic array (PLA)-controlled microprocessor is used. That is, the control microcode is stored in PLAs as opposed to read-only storage (ROS) or random-access memory (RAM), thus giving it the ability to perform many operations in parallel. The area of interest consists of PLAs whose outputs dot onto two separate but common buses, each of which feeds a bank of registers which can be referred to as the A and B controls registers 1 and
2. These registers are separated (logically) into unique fields where each field is dedicated to perform specific functions. For example, one field may be used to generate the necessary control lines used to gate register sources to the internal processor bus, while another field may be used to gate the processor bus to any one of many possible destinations. Some fields require decoders, such as decoders 3 and 4, on the outputs of the A and B controls registers to break each field up into unique control lines. This structure is then multiplexed by block 5 with the A and B phases of the internal CPU clocks (A phase gates the A controls register structure, B phase ..., etc.), thus generating a single set of unique control points.

The twelve control PLAs previously mentioned can be separated into three groups, designated SYS, EFA and EX, consisting of four PLAs each (A, B, C, D). Each group of PLAs is used to perform a given function; the System (SYS) PLAs control all exception conditions, interrupts, errors, and diagnostics; the Effective Address (EFA) PLAs are used to calculate the Effective Address for instructions and/or data, and the Execute (EX) PLAs are used to execute or perform a given instruction. Ideally these twelve PLAs could have been merged into three larger PLAs, thus reducing a large amount of chip area. However, in order to maintain a high level of performance and due to the fact that the access time through a large PLA would be longer, the PLAs...