Browse Prior Art Database

Clock Signal Generator

IP.com Disclosure Number: IPCOM000045191D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Wisgo, GD: AUTHOR

Abstract

The circuit in Fig. 1 allows, for example, a Motorola 68B54 advanced data link control module 10 to be interfaced to an Intel bus. Control module 10 requires that all input/output (I/O) activity be synchronous with respect to a system E clock signal. When interfacing the controller 10 to an bus, a single level of data buffering is required to hold the read data during an I/O read cycle. For such conditions, buffer control logic introduces additional delay and results in lost data. This problem can be solved by extending the E clock signal for I/O cycles.

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Clock Signal Generator

The circuit in Fig. 1 allows, for example, a Motorola 68B54 advanced data link control module 10 to be interfaced to an Intel bus. Control module 10 requires that all input/output (I/O) activity be synchronous with respect to a system E clock signal. When interfacing the controller 10 to an bus, a single level of data buffering is required to hold the read data during an I/O read cycle. For such conditions, buffer control logic introduces additional delay and results in lost data. This problem can be solved by extending the E clock signal for I/O cycles.

AND gate 12 performs a logical AND on the oscillator (OSC) signal and the chip select (CS) signal and generates the required gate signal to latch data into buffer 14. OR gate 16 performs a logical OR on the signal from AND gate 12 and the oscillator signal and provides the E clock signal to controller 10. As seen from Fig. 2, the E clock signal is extended until the end of the chip select pulse. This is the extension needed to hold the control data long enough for latching into buffer 14. Although data is latched for both the read and the write cycles, its output is only enabled during an I/O read select signal as detected by AND gate
18. Buffer 20 is also used for bus isolation purposes.

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