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Receiver Circuit

IP.com Disclosure Number: IPCOM000045234D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Crispi, FJ: AUTHOR [+3]

Abstract

The receiver circuits shown in Fig. 1 and Fig. 2 each utilize a 3.4 volt supply. The receiver circuit shown in Fig. 1 is designed to interface with 3.4 volt circuitry. The receiver circuit, shown in Fig. 2, is designed to interface with 5.0 volt circuitry.

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Receiver Circuit

The receiver circuits shown in Fig. 1 and Fig. 2 each utilize a 3.4 volt supply. The receiver circuit shown in Fig. 1 is designed to interface with 3.4 volt circuitry. The receiver circuit, shown in Fig. 2, is designed to interface with 5.0 volt circuitry.

Referring to Figs. 1 and 2, the operation of the circuit is as follows: If either IN1 or IN2 is at ground potential, node 1 is clamped at 0.6 V, transistor T is OFF and the output is at 1.7 volts.

When IN1 and IN2 are at 1.5 volts (Fig. 2) or 0.9 volt (Fig. 1), transistor T starts to conduct. The nominal threshold is 1.5 volts for the circuit shown in Fig. 2 and 0.9 volt for the circuit shown in Fig. 1. When transistor T is on (fully conducting), the output is at a 0.2 volt potential. The Schottky barrier diodes SBD 3 and SBD 4 clamp IN1 and IN2, respectively, at a -0.6-volt potential during undershoot condition.

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