Browse Prior Art Database

Static Latch with Multiple Input Ports

IP.com Disclosure Number: IPCOM000045242D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

Fig. 1 depicts a general form of a shift register latch (SRL) in a TTL (transistor transistor logic) Masterslice. For a more detailed discussion of shift register latches (SRLs) and their employment in level sensitive scan design (LSSD), see the references.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 70% of the total text.

Page 1 of 2

Static Latch with Multiple Input Ports

Fig. 1 depicts a general form of a shift register latch (SRL) in a TTL (transistor transistor logic) Masterslice. For a more detailed discussion of shift register latches (SRLs) and their employment in level sensitive scan design (LSSD), see the references.

It has been proposed that the slave latch L2, with only one input port may be simplified as shown in Fig. 2. If the system data input is not present, the master latch L1 may be simplified in a similar manner.

This article is directed to a simplification of the master latch L1, even if data inputs are from multiple sources. The objective is to contain, within the area of one logic cell, the full static latch of two-input ports (the conventional design shown in Fig. 1 requires four cells). The circuit schematic is shown in Fig.


3.

Notes relative to Figs. 3, 4 and 5 and a TTL Masterslice. 1. Referring to Fig. 3, T5 is provided to eliminate the possible

latch hazard associated with the system data input port.

if T5 is not used, a false down glitch may show up at '-L1'.

When '-L1' is UP, 'D' goes DOWN and 'C' goes UP. 2. Without TS, the latch hazard can also be eliminated by

designing 'C' to rise faster than 'A+C'. 3. This type of hazard will not affect the operations of

structured logic design, i.e., LSSD. 4. Multiple data inputs gated by the same clock 'C' can be

handled with multiple emitters on T1. 5. Extra pairs of clock and data can be dotted onto node '+L1',

if the 'A+C...