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NAND Latch for Large Gate Arrays

IP.com Disclosure Number: IPCOM000045243D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Maley, GA: AUTHOR [+2]

Abstract

The basic latch of Fig. 1 contains a well-known logic hazard. This hazard comes about from the two clock lines that drive block 1 and block 3. To compensate for this hazard, drive block D2 is designed to delay the clock signal to block 1. This delay insures that the feedback loop (2 to 3 to 2) is set before the input signal through block 1 is removed.

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NAND Latch for Large Gate Arrays

The basic latch of Fig. 1 contains a well-known logic hazard. This hazard comes about from the two clock lines that drive block 1 and block 3. To compensate for this hazard, drive block D2 is designed to delay the clock signal to block 1. This delay insures that the feedback loop (2 to 3 to 2) is set before the input signal through block 1 is removed.

However, when the delay in the logic circuits is small compared to the delay encountered by the line loading, line B must be at least as short, if not shorter, than line A or the delay in block D2 will be washed out. This requirement is getting more difficult to meet especially in large gate array chips.

Fig. 2 depicts a latch of the LSSD (level sensitive scan design) type that has the desirable characteristics needed for a large gate array chip. The latch input A DATA is for the relatively slower scan (testing) function, whereas input B DATA is for the relatively faster normal operation. Because of the increased delay in the clock network (adding D3 and D4 or any other type of delay), the clock lines are no longer a problem.

The input B (blocks 4 and 5) now forms a latch with blocks 2 and 3. This latch is highly conservative in design and has one very desirable characteristic. It is a hazard-free latch and any arbitrary delay can be inserted in any line. The latch will not fail to set to the proper value no matter what the combinations of the line delays are. This means that the pla...