Browse Prior Art Database

Set Reset Latch, Set Dominant

IP.com Disclosure Number: IPCOM000045244D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

A set dominant flip-flop is a well known logic design element. Conventional implementation requires approximately thirteen transistors. The disclosed latch requires only three devices. Fig. 1 employs FET devices. Fig. 2 employs bipolar devices. The operation is summarized as follows: SET RESET Q Comments 0 0 Q (unchanged, bit is latched) 0 1 0 (latch reset to zero) 1 0 1 (latch set to one) 1 1 1 (set dominates)

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Set Reset Latch, Set Dominant

A set dominant flip-flop is a well known logic design element. Conventional implementation requires approximately thirteen transistors. The disclosed latch requires only three devices. Fig. 1 employs FET devices. Fig. 2 employs bipolar devices.

The operation is summarized as follows: SET RESET Q Comments

0 0 Q (unchanged, bit is latched)

0 1 0 (latch reset to zero)

1 0 1 (latch set to one)

1 1 1 (set dominates)

In FET technology, R1 and R2 may be polysilicon strips or any load devices.

A reset dominant flip-flop may be provided by switching the connections to the source and gate of FET T1 of Fig. 1.

Referring to Fig. 2, a similar modification may be employed with bipolar transistors.

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