Browse Prior Art Database

TTL Gated Data Latch with Multiple Inputs

IP.com Disclosure Number: IPCOM000045245D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

In TTL (transistor transistor logic) masterslices, gated data latches with multiple inputs may be configured as shown in Fig. 1. If direct base couplings are used, this circuit can be simplified at the cost of performance and logic level compatibilities.

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TTL Gated Data Latch with Multiple Inputs

In TTL (transistor transistor logic) masterslices, gated data latches with multiple inputs may be configured as shown in Fig. 1. If direct base couplings are used, this circuit can be simplified at the cost of performance and logic level compatibilities.

Fig. 2 depicts a proposed improvement in the design of a TTL-gated data latch. In Fig. 2, node CE is tied to the latch output node Q. If node CE were connected to ground, the UP level of node CP is clamped too low. Node CP feeds both the T2 base and T3 base. Base current may be hogged by one of the two transistors. However, current hogging will not impact latch operations. Hogging occurs only when Q and Dl are low and C1 is high. If T2 hogs base current, T3 is not hard On and T4 may not be Off, but under this condition T4 need not be Off. If T3 hogs base current, T2 may not be hard On, but under this condition Q will float up to release the hogging.

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