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Browse Prior Art Database

Driver Circuits

IP.com Disclosure Number: IPCOM000045247D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Barish, AE: AUTHOR [+4]

Abstract

The driver circuits shown in Fig. 1 through Fig. 5 each utilize a 3.4-volt supply. The circuit shown in Fig. 4 is designed to interface with 5.0-volt circuitry. The circuits shown in Figs. 1, 3 and 5 are designed to interface with 3.4-volt circuitry. The circuit shown in Fig. 2 is designed to interface with both 5.0-volt circuitry and 3.4-volt circuitry.

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Driver Circuits

The driver circuits shown in Fig. 1 through Fig. 5 each utilize a 3.4-volt supply. The circuit shown in Fig. 4 is designed to interface with 5.0-volt circuitry. The circuits shown in Figs. 1, 3 and 5 are designed to interface with 3.4-volt circuitry. The circuit shown in Fig. 2 is designed to interface with both 5.0-volt circuitry and 3.4-volt circuitry.

Referring to Fig. 1: If both the Inhibit node and Data node are at ground potential, the three-state push-pull driver is in the high-impedance state. If the Inhibit node is disconnected from the base of transistor T3, the three-state push- pull driver becomes a push-pull driver. In the push-pull mode if the Data node is at a ground potential, transistor T1 is OFF, node 2 is pulled-up to approximately
3.4 volts through resistor R3 turning on transistors T3 and T4 (Darlington pair), resistor R5 limits the current in transistor T4, and node Out is at a nominal up- level (1.8 volts). With the Data node at 1.6 volts, transistors T1 and T2 are on and node Out is at 0.2 volt. The feedback capacitor C controls the rate of change of voltage at node Out.

Referring to Fig. 2: With node In at ground potential, transistor T1 is OFF and node Out is at a nominal up-level determined by the external pull-up resistor (not shown). With node In at 1.6 volts, transistors T1 and T2 are ON and node Out is at 0.2 volt. The feedback capacitor C controls the rate of change of voltage at node Out.

Referring to Fig. 3: With...