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High Speed Hardware Based Diagnostic System for High Speed Digital Subsystems

IP.com Disclosure Number: IPCOM000045253D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 4 page(s) / 56K

Publishing Venue

IBM

Related People

Landon, TV: AUTHOR [+2]

Abstract

An effective approach is provided for testing high speed subsystems with minimal processor involvement. This is achieved by using a simple programming scheme to detect and resolve problems associated with high speed digital subsystems used in relatively sophisticated processing systems. Such an approach permits great latitude in the generation and design of diagnostic test patterns.

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High Speed Hardware Based Diagnostic System for High Speed Digital Subsystems

An effective approach is provided for testing high speed subsystems with minimal processor involvement. This is achieved by using a simple programming scheme to detect and resolve problems associated with high speed digital subsystems used in relatively sophisticated processing systems. Such an approach permits great latitude in the generation and design of diagnostic test patterns.

In large digital systems where subsystems provide major processing functions, the system controller or host computer generally has much slower data rates than the subsystem with which it must communicate. The results of this mismatch, when the host computer is called upon to perform subsystem diagnostics, is a diagnostic system which is inefficient, cumbersome and ineffective in resolving subsystem failures, particularly those failures that occur when the subsystem is running at its normal or intended speed. The disclosed high speed hardware based diagnostic system will allow diagnostic data patterns to be supplied to, and the results extracted from, the subsystem at subsystem speeds. In addition, this hardware based concept provides great latitude to the diagnostician in the design and versatility of diagnostic procedures. The approach employed enables the diagnosing of faults which only appear at full and/or normal systems operation. Moreover, the scheme permits a limitless number of potential diagnostic patterns. The ease with which diagnostic patterns (as well as real patterns) may be processed for use in this system permits rapid resolution of difficult subsystem problems. Not only does the diagnostic system have the advantage of great speed and versatility, it also gives the subsystem design engineer the capability of testing the subsystem more rigorously than would be possible using conventional diagnostic approaches. This is made possible because the subsystem engineer is not required to have programming knowledge to design data patterns that would be appropriate for a given subsystem. The only system programming tasks that need be performed by the host computer are those required to set subsystem modes (i.e. initialization, error recovery, etc.).

With reference to Fig. 1, diagnostic data patterns are created off line with a large and/or small computer system. Real data patterns, usually residing in pattern libraries as shown at 1, may be transferred via computing system 3 to small computer system 5. The small computer system writes data into programmable device 7 comprising EPROMs (Electrically Programmable Read- Only Memories) , PROMs, or like devices. These programmable devices (now programmed) are then placed in the subsystem diagnostic sections 9, as shown in Fig. 2.

The host computer 11, shown in Fig. 2, sets the mode of operation for the subsystem 13 under test, and retrieves and logs out error and subsystem status. The operation of the hardware based diagnosti...