Browse Prior Art Database

Sample and Hold Type Mark Detector

IP.com Disclosure Number: IPCOM000045271D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Eguchi, H: AUTHOR

Abstract

A circuit for sensing optical marks on a reflective background is disclosed which is applicable to an optical line finder (OLF) for passbook printing, wherein a line mark for the last printed line thereon is optically sensed prior to the next line printing to properly determine the next print line.

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Sample and Hold Type Mark Detector

A circuit for sensing optical marks on a reflective background is disclosed which is applicable to an optical line finder (OLF) for passbook printing, wherein a line mark for the last printed line thereon is optically sensed prior to the next line printing to properly determine the next print line.

Due to repeated passbook handling, the background reflectivity of the print medium may be degraded, and also the density of the printed optical line marks may be varied by ink ribbon life and passbook handling. To meet the wide range of reflectivities, the line mark sensing is desired to be based on the transition of the relative reflectivity rather than the absolute reflectivity.

Referring to the drawing, the sensing device is a phototransistor Q in combination with an LED (light emitting diode) in a reflective sensing mode. The photo current in the transistor Q increases as the reflected light from the medium increases. This current is linearly amplified by a voltage converter and supplied to a discriminator. The voltage converter output signal is also supplied to a sample and hold (S&H) circuit, causing the signal level to be held in the voltage buffer, and further to be supplied to the input of the discriminator as a threshold voltage through a voltage divider.

As the passbook is fed into the station, its reflective background is sensed to cause a high photo current and a proportionally high voltage at the voltage converter output. A capacitor C of the S&H circuit is charged at that level. The voltage across the capacitor C is buffered with a high impedance voltage buffer and applied to the negative input of the discriminator through a resistive voltage divider. This establishes the mark sensing threshold as a consta...