Browse Prior Art Database

Altered Bit Correction

IP.com Disclosure Number: IPCOM000045273D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 18K

Publishing Venue

IBM

Related People

Takano, A: AUTHOR

Abstract

A single-bit error correction method is disclosed where the check bits are generated by XORing the binary digits representing the "1" data bit location. This code is suitable for data of serial configuration.

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Altered Bit Correction

A single-bit error correction method is disclosed where the check bits are generated by XORing the binary digits representing the "1" data bit location. This code is suitable for data of serial configuration.

Check bits are generated as follows. Binary representations of bit locations of "1" bit in a data block are XORed to obtain the first check bits C1. Further, the second check bits C2 are generated by XORing the binary representations of "1" bit locations in the above first check bits C1. Thus, the second check bits are the check bits for the first check bits. The data block and the first and the second check bits are stored or transmitted through the communication line in the format shown below.

DATA C1 C2.

If the received data has a single error, the error is corrected as follows. The first syndrome is generated from the data and the check bits C1, and the second syndrome is generated from the check bits C1 and C2. This is done by XORing, for example, the received check bits and the check bits regenerated from the received data bits. In the case that the second syndrome indicates that there is no error in C1 or C2, a single error in the data would be corrected with the first syndrome. In the case that both the first and the second syndromes indicate the existence of an error, such a single error will be located in the check bits C1.

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