Browse Prior Art Database

Microcomputer Control of Sequences

IP.com Disclosure Number: IPCOM000045284D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 59K

Publishing Venue

IBM

Related People

Pearson, KA: AUTHOR

Abstract

Control sequences to a device or process require variations of some basic pattern or a variety of different patterns. For example, brightness of an AC Plasma Display Panel depends inter alia upon the frequency of the sustain signal. Two representative sequences for the sustain signals applied to the horizontal and vertical drive lines are illustrated in Fig. 1. While these and other sequences may be stored in a ROS (Read-Only Storage) or RAM (Random-Access Memory) directly, a more efficient technique for handling a large number of such sequences utilizes two RAMs, as described herein. Since only one sequence is active at any one time, only the active sequence needs to be immediately available, e.g., from RAM #1.

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Microcomputer Control of Sequences

Control sequences to a device or process require variations of some basic pattern or a variety of different patterns. For example, brightness of an AC Plasma Display Panel depends inter alia upon the frequency of the sustain signal. Two representative sequences for the sustain signals applied to the horizontal and vertical drive lines are illustrated in Fig. 1. While these and other sequences may be stored in a ROS (Read-Only Storage) or RAM (Random- Access Memory) directly, a more efficient technique for handling a large number of such sequences utilizes two RAMs, as described herein. Since only one sequence is active at any one time, only the active sequence needs to be immediately available, e.g., from RAM #1. If conditions change, a new sequence can be constructed in RAM #2 from an algorithm contained in a microcomputer, while the device remains under control of the outputs from RAM #1.

As shown in Fig. 2, while microcomputer 3 is being used to address and write RAM #2, the present sequence is being derived from RAM #1 and SELECT line 5 is low or deselected, enabling the outputs from RAM #1 to control the device. An input 7 to the microcomputer, requiring a change to the control sequence, causes an algorithm in microcomputer 3 to generate the new sequence in RAM #2. When the END OF SEQUENCE line 9 becomes active, the control program contained within microcomputer 3 switches the SELECT line 5 high whereby RAM #2 outputs are enabled to control the device as the microcomputer addresses and writes RAM #1 when the next change is received. The designation M defines the number of address bits used to address the RAM, while the designation N defines the width of the RAM, a typical width being 8 or 16 bits. Inverter 13, together with associated select line 5, selects which the RAM #1 and #2 and their respective output gates 15 and 17, respectively, are to be operated. Similarly, inputs are labeled by the functions to be performed and the associated number of conductors or circuits. Logical OR circuit 19 directs the end of sequence signal from RAM #1 or #2 to microcompu...