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Self Testing Scheme Using Register Latches

IP.com Disclosure Number: IPCOM000045296D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Bottorff, PS: AUTHOR [+4]

Abstract

The shift register latches (SRLs) 10 are connected to function both as a linear feedback shift register (LFSR) to generate pseudo-random patterns to be applied to the chip inputs as well as a signature analyzer for the network outputs. An example of such a dual-function register is shown in Fig. 1.

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Self Testing Scheme Using Register Latches

The shift register latches (SRLs) 10 are connected to function both as a linear feedback shift register (LFSR) to generate pseudo-random patterns to be applied to the chip inputs as well as a signature analyzer for the network outputs. An example of such a dual-function register is shown in Fig. 1.

The input connection in Fig. 1 to apply the patterns generated in the SRLs assumes that all chip inputs can be set to the non-controlling state by forcing all drivers feeding them to the non-controlling state. Otherwise, a multiplexer has to be inserted between the chip inputs and the logic. Testing is then done as follows (see Fig. 2): (i) Set g1 g2=10. (ii) Scan in initial seed for random pattern generation. This seed also serves as first test pattern. (iii) set g1 g2=01 for logic test. (iv) Apply pattern. (v) Apply system clock- sequences to embedded SRLs, if any, for signal propagation through them. (vi) Apply A, B clocks for output hashing/next pattern generation. (vii) Return to step (iv) until enough patterns have been applied.

Note that in this method the embedded SRLs are not being scanned during the test nor are they being used for pattern generation/output hashing.

Note that in the above testing procedure, pattern generation/ output hashing is done using the scan clocks A, B, thus leaving the system path through the SRLs untested. This can, however, be tested as follows: First, g1 and g2 are set to 1 and 0, respecti...