Browse Prior Art Database

Micromapper

IP.com Disclosure Number: IPCOM000045301D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 67K

Publishing Venue

IBM

Related People

Bipes, RA: AUTHOR [+2]

Abstract

The micromapper 20 is a hardware tool for measuring the effectiveness of the test of a microprocessor-based system 10. The micromapper 20 includes a microprocessor 25 which is connected to control logic 30. Control logic 30 in turn is connected to read/write memory 50. The read/write memory 50 is connected to the system under test 10 via active probes 60 which are part of the micromapper 20.

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Micromapper

The micromapper 20 is a hardware tool for measuring the effectiveness of the test of a microprocessor-based system 10. The micromapper 20 includes a microprocessor 25 which is connected to control logic 30. Control logic 30 in turn is connected to read/write memory 50. The read/write memory 50 is connected to the system under test 10 via active probes 60 which are part of the micromapper 20.

The probes 60 provide isolation of micromapper 20 from the system 10 and adapt the logic levels of system 10 to the logic levels of micromapper 20. Whenever a micro-instruction is fetched in system 10, a bit is set in the read/write memory 50. Microprocessor 25 reads the bits from memory 50 to determine which micro-instructions in system 10 were executed. Microprocessor 25 includes a keyboard and display, tape cartridge drive and printer for displaying, recording and printing test information.

The address bus 15 of the system under test 10 is connected to probes 60, and, in this example, there are 16 pairs of lines. If any of the 16 lines is not used, the unconnected probe leads are equivalent to a probe input of a voltage lower than the threshold voltage. The probes 60 connect to converter 31 (Fig. 2) of control logic 30 which converts emitter-coupled logic (ECL) signals to transistor to transistor logic (TTL) signals. The output of converter 31 is applied via select circuit 32 to latches 33. The outputs of latches 33 provide a T16-bit address to memory 50. Digital-to-analog converter 70 sets the threshold level of the probes 60 under microprocessor control by providing an analog threshold select signal to them.

The clock signal of the system under test 10 is applied to one of the probes 60 and its output, the MAP CLK, is applied to converter 34 which functions to perform a conversion in the same manner as converter 31. The MAP CLK signal on line 42 synchronizes the micromapper 20 to the system under test 10. It indicates each instruction fetch in system 10. The outputs of converter 34 are applied to select logic 35. Select logic 35 also receives a Controller Strobe signal on line 41 and a CLK Polarity signal on line 39. The Controller Strobe signal has the ame function and operatio...