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Optical Probing and Testing Technique for Light Sensitive Electrical Devices

IP.com Disclosure Number: IPCOM000045342D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Chi, CC: AUTHOR [+4]

Abstract

Semiconductor or superconductor devices may be tested one at a time without electrically probing each device individually by optically probing each device with a light intensity sufficient to nondestructively affect the electrical transport mechanism of the device and then observing the effect the light probe has at some common and remote electrical point or points.

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Optical Probing and Testing Technique for Light Sensitive Electrical Devices

Semiconductor or superconductor devices may be tested one at a time without electrically probing each device individually by optically probing each device with a light intensity sufficient to nondestructively affect the electrical transport mechanism of the device and then observing the effect the light probe has at some common and remote electrical point or points.

Modern LSI and VLSI (very large-scale integration) contains a large number of devices on a single chip. It is obviously impossible to have probing or testing leads for each of them. However, for diagnostic purposes, it is desirable and helpful to know the position or distribution of failed or potentially troublesome devices. We propose to use a simple optical scanning technique to locate the bad devices on a chip without adding many more voltage leads. This technique works for light-sensitive devices in general, either semiconductive or super conductive, discrete or two-dimensional contnuum. Since there are some technical differences in each case, this optical probing and testing technique will be described by way of example. (1) Discrete Semiconductive Devices.

Usually semiconductive devices use a parallel fan-out scheme
i.e., many devices in parallel, which is symbolically depicted in Fig. 1. There may be many internal interconnections among the devices, which cannot be probed individually, but for each parallel-powered set, in addition to the powered lead I(o), there are usually a common voltage output lead V (out) and a common signal input lead V (in) accessible from the outside. In order to test individual devices like these, we propose to cool down the chip to low temperature so that the devices become nearly open due to the carrier's freezing-out. Then, a focused laser beam (pulsed or CW) is used to scan the individual devices. Laser power is adjusted to give the desired level of carrier concentration to make the device function properly. Thus, the uniformity of the device characteristic can be mapped out without having individual voltage leads. A common cryogenic cold finger dewar with an optical window is adequate for cooli...