Browse Prior Art Database

Or Gate Using Resistive Isolation in Jospehson Technology

IP.com Disclosure Number: IPCOM000045347D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 43K

Publishing Venue

IBM

Related People

Heidel, DF: AUTHOR [+2]

Abstract

Providing an input bridge of resistors and Josephson junctions permits an OR-gate to use resistive isolation, with improved margins and higher speeds, and with a fan-out of two. Fig. 1 shows the OR-gate. The mode of operation is as follows.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 3

Or Gate Using Resistive Isolation in Jospehson Technology

Providing an input bridge of resistors and Josephson junctions permits an OR-gate to use resistive isolation, with improved margins and higher speeds, and with a fan-out of two.

Fig. 1 shows the OR-gate. The mode of operation is as follows.

Initially the gate current biases junctions j(1), j(2), j(3), j(4) and j(5) in the superconducting state. The current I(g1) splits equally between the branches containing j(1) and j(2), the resistors in both branches being equal. Currents I(g2) I(g3) and I(g4) bias junctions j(3), j(4) and j(5), respectively. When control current I(c)arrives, gate and control currents add in the branch containing J(2), switching J(2).

We note that except for the fact that the critical currents of J(1) and J(2) are the same, and the resistors in the corresponding branches are of the same value as R (for improved margins), the mode of operation described so far is similar to the "isolator" stage of the DCL (Direct Coupled Logic) OR-gate.

After J(2) switches, however, the mode of operation is different from the DCL OR-gate. The coupling resistor between J(2) and J(3) is "small," typically 0.5 ohm. This results in J(3) being the next junction to switch. Subsequently, J(4) switches. At this time the net current through J(1) is large enough to switch J(1), isolating the gate and control currents. Finally, J(5) switches, and the gate current is steered into the load resistors, providing a fan-out of two.

Fig. 2 is a plot of computed variables against time.

In the statistical extreme case of high currents and low I(0)s, J(1) switches after J(2) and J(3) have switched and then J(4) and J(5) switch. For low cu...